Energy storing memory circuit

ABSTRACT

The invention relates to a memory arrangement having an energy storage device (store) which collects the energy transported during the flowing of a write or read current and makes it available for a new write or read operation.

FIELD OF THE INVENTION

The present invention relates generally to memory devices. Inparticular, the present invention relates to a random access memoryarchitecture.

BACKGROUND

Information is written to memory cells, in particular MRAM memory cells,by electric currents which flow from a constant-current source withrespect to a fixed potential, such as, in particular, ground. Dependingon their direction, these currents bring about a parallel orantiparallel orientation of the polarization of magnetoresistive layersthat are separated by a tunnelling barrier layer within an individualmemory cell of the MRAM array. As is known, a parallel orientation ofthe polarization is assigned a lower resistance than an antiparallelorientation of the polarization. Pulses are used for write currents, thepulse amplitude rather than the pulse duration being critical for thewrite operation.

During a write operation to a selected memory cell at the crossoverbetween a specific word line and a specific bit line, in addition tomagnetic energy, electrical energy is also converted into thermalenergy, and thus consumed, as a result of the voltage drop across theline resistances of the word line or bit line. Overall, the energybalance (or “efficiency”) is extremely unfavourable since a large partof the electrical energy is transformed into heat.

In addition to this energy loss, measures have to be taken so that thevoltage drop across individual memory cells of memory cell arrays ofvarying sizes is kept uniform.

Moreover, when reading from a memory cell, a current pulse specifyingthe stored information flows, wherein the current pulse has a largeramplitude in the case of a lower resistance (parallel orientation of thepolarization) than in the case of a higher resistance (antiparallelorientation of the polarization) and can thus represent a cell contentas “1” or “0”. In a similar manner to a write current, such a currentpulse brings about an energy loss in the form of heat.

Hereinafter, the writing to and reading from a memory cell in a memorycell array of the memory arrangement will also be referred to as“addressing” or “setting”.

As described below previous attempts at addressing this energy lossproblem have not yielded promising results.

As is known, the interconnect resistance of a word line, bit line, oradditional write line is determined by the specific conductivity of theinterconnect material, the interconnect cross-sectional area and length.To avoid excessively large voltage drops across memory cells in a memoryarrangement (also hereinafter referred to as a “memory circuit”) andthus to reduce the risk of electrical breakdowns, the interconnects aredesigned with the least possible resistance, and the residual voltageremaining after setting is “consumed” in resistors connected downstream.In other words, losses in the interconnects and, in particular, in theresistors connected downstream are thus deliberately accepted. Thismeans, however, that the energy balance is highly unfavourable in thecase of such existing memory arrangements.

SUMMARY

Embodiments of the present invention provide a memory circuit in whichenergy losses are minimized, so that an improved energy balance isobtained.

In an exemplary embodiment, a memory circuit having at least one memorycell array containing a plurality of memory cells connected to bit linesand word lines and, if appropriate, additional write lines, contains atleast one generator device. The generator device is designed as anenergy storage system that collects the energy liberated during asetting operation (in particular a write operation) of at least onememory cell, so that the energy is not “consumed” in a resistor, butrather is available for subsequent write or read operations.

In a preferred embodiment, an MRAM memory array is connected to agenerator device designed as an energy storage system which, when amemory cell is addressed (or set), collects the energy transported bythe current flowing in the addressing process, so that the energy isavailable for subsequent addressing of memory cells.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a memory circuit comprising a multiplicity of MRAMmemory cells arranged according to an exemplary embodiment of thepresent invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The following list of symbols is used consistently throughout the textand drawings.

LIST OF REFERENCE SYMBOLS

1 Memory cell array

2-5 Generator devices

Mux2-Mux5 Multiplexers

E2-E5 Energy storage units

S Switch pair

C1, C2 Capacitors

M Memory for spins

Rf Reflector for spin waves

C Central control unit

L Inductance

SLe Voltage-carrying line

WL1-WLm Word lines

BL1-BLn Bit lines

x2-x5 Compensation energy stores

Iwrite Write current

FIG. 1 illustrates a memory circuit arranged according to an exemplaryembodiment of the present invention. In this case, the individual memorycells or resistors Rc comprise so-called MTJ (MTJ=magnetic tunneljunction ) layer sequences in which a tunnel layer is located betweentwo magnetoresistive layers.

In circuit 100, each individual resistor (Rc) 102 lies between a wordline (WL) 104 and a bit line (BL) 106. A total of m word lines 104 and nbit lines 106 are provided in the memory cell array 1. A selected cell110, represented by a black filled-in resistor Rc, lies for examplebetween word line 104, designated as WL3, and the bit line 106,designated as BL3. Cell 110 is selected by a specific voltage differencebeing applied to word line WL3 and bit line BL3.

A generator device in the form of an energy storage system 2, 3, 4, 5 isprovided on each side of memory cell array 1. These energy storagesystems 2, 3, 4, 5 each comprise an energy storage unit 112 (E2), 113(E3), 114 (E4) and 115 (E5), respectively, and a multiplexer 122 (Mux2),123 (Mux3), 124 (Mux4) and 125 (Mux5). Energy storage system 2, forexample, comprises energy storage unit 112 and the multiplexer 122.

Each energy storage unit 112-115 comprises capacitors 131 (C1), 132(C2), which can be converted from a series circuit into a parallelcircuit by means of a switch pair 134 (S). In this case, the energystorage unit 112 has a parallel circuit of capacitors 131 and 132, whileenergy storage unit 114, which is connected to energy storage unit 112via word lines 104, has a series circuit comprising correspondingcapacitors 131, 132. Correspondingly, capacitors 131, 132 of energystorage unit 113 are configured, by means of the switch pair 134, in aparallel circuit and the capacitors 131, 132 of energy storage unit 115,which is connected to the energy storage unit 114 via bit lines 106, areconfigured in a series circuit. In other words, word lines 104 and thebit lines 106 are each provided with an energy storage unit in each caseat their mutually opposite ends, with capacitors connected in a seriescircuit at one end and capacitors connected in a parallel circuit at theopposite end. The switches 134, which preferably comprise transistors,such as, in particular, MOS transistors, can be driven by a centralcontrol unit 140 (C), as is indicated diagrammatically for switch pair134 of energy storage unit 113.

The series and parallel circuits of capacitors 131 and 132 are put atfixed potential, for example ground, at the end not connected to therespective multiplexers.

Instead of capacitors, energy storage units 112-115 may also have otherenergy stores, such as, for example, memories 160 (M) for spins andreflectors 170 (Rf) for spin waves or inductances 180 (L). However,energy storage units constructed from capacitors are preferably used. Itis also possible for there to be more than two capacitors in each casein a parallel circuit or a series circuit.

Multiplexers 122, 123, 124, 125 may also be provided in each case with acompensation energy store 142 (x2), 143 (x3), 144(x4) and 145 (x5),which can compensate for energy losses that possibly occur and can beconnected in by the corresponding multiplexer, under the control of thecontrol unit 140. Instead of such a compensation energy store, it isalso possible, if appropriate, to provide a voltage-carrying line 150(SL), as is shown by way of example for the multiplexer 125.

As is known, information is written to MRAM memory cells 102, forexample, by means of electric currents. In such case, currents usuallyflow from a constant-current source with respect to ground, causingresistance losses so that the energy balance is unfavourable overall.

In exemplary embodiments of the present invention, the interconnects ofword lines 104 and bit lines 106 are composed of a material with theleast possible bulk resistance, so that inherently comparatively littleelectrical energy is converted into heat.

Preferably, the flowing electrical energy which is output, for example,from energy storage unit 115 and from the energy storage unit 114 is not“consumed” in resistors, but rather can be stored in the energy storageunits 113 and 112, respectively. In other words, energy storage units114 and 115 using the series circuits of capacitors 131, 132, act as asource of a write current (I_(write)) which flows from energy storageunits 114, 115 into energy storage units 112 and 113, respectively, andis taken up and stored there by capacitors 131, 132 which are connectedin a parallel circuit.

The sources of electrical charges formed by the series circuits ofcapacitors which are discharged via the interconnects of word lines 104or bit lines 106 into corresponding energy storage units comprisingparallel circuits of corresponding capacitors. The transport of chargesis linked with a magnetic field with which the MRAM memory cells can beswitched in a known manner. In the exemplary embodiment of the presentinvention illustrated in FIG. 1, word line WL3 and bit line BL3 aredriven via the multiplexer pairs 122, 124 and 123, 125, respectively, sothat a corresponding write current flows through these lines to thememory cell 110.

Multiplexers 112-115 can in each case be changed over by the centralcontrol unit 140 in a clock- and pulse-controlled manner, so that,overall, the number of sources and sinks of charges that is required isno more than the number of constant-voltage sources and series resistorsthat has been required heretofore in existing memory arrangements.

The series circuit of the capacitors 131, 132 is to be regarded as acharge source since it has double the voltage of the individualcapacitors at its output, while a parallel circuit of these capacitorssupplies only a single voltage. Thus, if the two circuits, that is tosay a series circuit and a parallel circuit, are linked with one anotherat opposite ends of the word lines or bit lines, then a chargeequalization current flows from the series circuit into the parallelcircuit. A switch pair or other suitable device can convert the seriescircuit to a parallel circuit, so that a source becomes a sink, and viceversa. Charge equalization thus takes place in the respective oppositedirection.

If appropriate, the multiplexers 122-125 may also be configured andinterconnected in such a way that currents flow through theinterconnects of the word lines and bit lines always in the samedirection.

The compensation energy store in the form of the additional capacitors142-145 is provided in order to compensate, after writing, for energylosses on account of the magnetic field and the interconnect resistancein the case of the respective parallel circuit. In other words, if, forexample, a write current I_(write) flows from the energy storage unit115 to the energy storage unit 113, then the loss occurring in theprocess is compensated for by the additional capacitor 143. Instead ofsuch an additional capacitor, the voltage-carrying line 152 (Sle) canalso be used, if appropriate.

In the above exemplary embodiment, the energy storage units comprisecapacitors. In other embodiments of the present invention, othersuitable energy stores can also be used for this purpose, as indicateddiagrammatically in FIG. 1, for example, by spin memory 160, spinreflector 170 and coil 180.

Memory circuit 100 is preferably employed an MRAM circuit. However, inother embodiments of the present invention, memory circuit 100 can alsobe used in other types of memory.

Moreover, in embodiments of the present invention, it is not necessaryfor an energy storage unit with a multiplexer to be provided at eachside of a memory cell array. Rather, it is also possible to equip, forexample, only word lines 104 or only bit lines 106 with correspondingenergy storage units and multiplexers.

The multiplexers themselves are preferably configured in such a way thatthey allow the driving of a word line or bit line associated with aselected memory cell, so that the I_(write) flows only through therespective corresponding word line or bit line. The same appliescorrespondingly to a read operation.

Accordingly, embodiments of the present invention comprise a memorycircuit constructed with generator devices for storing energy used inmemory operations, thereby minimizing energy loss and improving theenergy balance. The generator device may comprise four generator units,each of which is located at one side of the memory cell array and isconnected to the word lines or bit lines via multiplexers.

In exemplary embodiments of the present invention, the generator unitsmay be able to be changed over in a clock- or pulse-controlled mannerand thus serve as clock- or pulse-controlled charge sources. Transistorsare preferably used for the clock- or pulse-controlled changeover.

The generator units each have energy storage units, for which anydesired combinations of capacitors, inductances or other storage designscan be used. Such designs may be, in particular, novel energy storessuch as memories for spins in semiconductors or reflectors for spinwaves. Memories for spins exploit the fact that spins can be preservedfor a very long time, and are regarded as promising magnetoelectroniccomponents. The use of capacitors in energy storage units isparticularly advantageous, however, since they can readily be integratedand realized in a simple manner.

If capacitors are used in the energy storage units, the capacitors maybe changed over from a parallel circuit of at least two capacitors intoa series circuit of said two capacitors by clock- or pulse-controlledchangeover of at least one switch pair. By way of example, if a seriescircuit of two capacitors is located at one end of a bit line and aparallel circuit of two corresponding capacitors is located at the otherend of the same bit line, then a write current flows from one end of thebit line to the other end of the bit line via the respective selectiontransistors. If the series circuit at the one end of the bit line isthen changed over into a parallel circuit of the two capacitors and ifthe parallel circuit of the two capacitors at the other end of the bitline is switched to a series circuit of these two capacitors, then thearrangement is ready to generate a current pulse again.

Additional compensation energy stores may also be provided, which areconstructed in a similar manner to the energy storage units and cancompensate for energy losses arising after a setting operation of atleast one memory cell. These additional compensation energy stores canbe connected to word lines or bit lines via the respective multiplexers,so that it is possible to compensate for energy losses that occur, ifappropriate, by connecting in these compensation energy stores.

Like the energy storage units, the compensation energy stores likewisepreferably comprise capacitors.

The foregoing disclosure of the preferred embodiments of the presentinvention has been presented for purposes of illustration anddescription. It is not intended to be exhaustive or to limit theinvention to the precise forms disclosed. Many variations andmodifications of the embodiments described herein will be apparent toone of ordinary skill in the art in light of the above disclosure. Thescope of the invention is to be defined only by the claims appendedhereto, and by their equivalents.

Further, in describing representative embodiments of the presentinvention, the specification may have presented the method and/orprocess of the present invention as a particular sequence of steps.However, to the extent that the method or process does not rely on theparticular order of steps set forth herein, the method or process shouldnot be limited to the particular sequence of steps described. As one ofordinary skill in the art would appreciate, other sequences of steps maybe possible. Therefore, the particular order of the steps set forth inthe specification should not be construed as limitations on the claims.In addition, the claims directed to the method and/or process of thepresent invention should not be limited to the performance of theirsteps in the order written, and one skilled in the art can readilyappreciate that the sequences may be varied and still remain within thespirit and scope of the present invention.

1. A memory circuit for reduced energy loss comprising: a memory cellarray containing a plurality of memory cells, each memory cell connectedto a word line and bit line; and at least one generator deviceconfigured to feed a current into a bit line and/or wordline assigned toa memory cell during reading or writing the memory cell, wherein thegenerator device comprises an energy storage system that collects theenergy transported by the current flowing during an addressing process,so that the energy is available for subsequent addressing of memorycells.
 2. The memory circuit of claim 1, wherein the energy storagesystem is configured to change over between an energy take-up state andan energy release state in a clock-controlled manner.
 3. The memorycircuit of claim 1, wherein the energy storage system comprises energystorage units arranged on opposite sides of the memory cell array. 4.The memory circuit of claim 1, wherein an energy storage unit isconstructed from capacitors and/or inductors.
 5. The memory circuit ofclaim 3, wherein the energy storage unit is constructed from memoriesfor spins in semiconductors and reflectors for spin waves.
 6. The memorycircuit of claim 4, wherein the capacitors are connected to a switchdevice configured to change the arrangement of the capacitors to or froma parallel circuit of at least two capacitors into a series circuitthereof.
 7. The memory circuit of claim 1, wherein the energy storagesystem is connected to the memory cell array via multiplexers.
 8. Thememory circuit of claim 1, further comprising: at least one compensationenergy store or voltage-carrying line, whereby energy losses arisingbefore, during and after writing to or reading from a memory cell arecompensated.
 9. The memory circuit of claim 8, wherein the compensationenergy store is constructed from at least one capacitor and/or at leastone inductor.
 10. The memory circuit of claim 8, wherein thecompensation energy store is constructed from at least one memory forspins in semiconductors and at least one reflector for spin waves. 11.The memory circuit of claim 1, wherein the memory cell array is formedby an MRAM array.
 12. A memory architecture for reducing energyconsumption in memory operations comprising: a memory array containingmemory cells addressable by bit lines and wordlines; at least one pairof energy storage units for storing and delivering energy to the memoryarray that is used in addressing operations, wherein each energy storageunit of the pair lies on an opposite side of the memory array from theother storage unit; and a multiplexer coupled to the energy storagedevice such that energy can be delivered to and from individualwordlines or bitlines used to address a memory cell.
 13. The memoryarchitecture of claim 12, wherein each energy storage unit comprises atleast two capacitors that be alternately arranged as a series capacitorcircuit or as a parallel capacitor circuit by means of a switch.
 14. Thememory architecture of claim 13, further comprising a central controlunit to control change over of multiplexers and to drive the switches inthe storage units.
 15. The memory architecture of claim 12, whereinenergy traveling to and from the memory array is stored in storage unitscontaining spin memories, spin wave reflectors, or inductors.
 16. Thememory architecture of claim 12, further comprising at least onecompensation energy store, each store comprising a capacitor tocompensate for energy losses due to a magnetic field or interconnectresistance.
 17. The memory architecture of claim 13, wherein the memoryarray is an MRAM array.
 18. The memory array of claim 13, wherein thememory array is a DRAM array.
 19. The memory array of claim 12, whereinthe wordline and bitline interconnects are comprised of material with aminimum bulk resistance.